In the case of semiconductor memory components, a top of a semiconductor body or substrate made of semiconductor material holds a memory cell array comprising memory cells each of which has a transistor structure and is addressed using word lines and bit lines. Programming, reading and erasing are performed using a logic circuit in an actuation peripheral area. This circuit is normally constructed using CMOS transistors. Although the actuation components and the memory cells have a homogeneous transistor structure in principle, the transistors in the logic circuit need to have a special gate dielectric (gate oxide) provided on the top of the semiconductor body, while the memory cells require a memory layer or memory layer sequence for the programming operation. Such a memory layer may be a floating gate electrode, for example, which is embedded in dielectric material between the gate electrode and the channel region of the transistor in question.
In the case of charge trapping memory cells, the gate dielectric provided is a layer sequence that has a memory layer between limiting layers. The memory layer is dielectric material, but may also be intrinsically conductive (undoped) silicon. Such a cell is programmed by injecting hot, i.e., energy-rich, electrons from the channel region through the bottom-limiting layer of the memory layer sequence into the memory layer. Such memory cells are known as SONOS memory cells, in which the memory layer sequence comprises a nitride layer as memory layer between limiting layers made of oxide.
A limiting layer made of oxide in the memory layer sequence cannot normally be used as gate oxide for the transistors in the actuation peripheral area. It is, therefore, necessary to produce separate oxide layers or other dielectric layers for the transistors in the memory cell array and for the transistors in the actuation circuit.
Fabrication processes customary to date first of all involve the memory layer or memory layer sequence being produced on the top of the semiconductor body over the entire area. Outside the memory cell array, this memory layer is removed. In the case of an oxide/nitride/oxide memory layer sequence, this is preferably done by wet chemical means, because this is the best way of preventing damage to the semiconductor body as a result of etching the surface. In principle, this etching may also be performed using a dry etching process; in this case, however, the problem of possible substrate damage arises.
The memory layer sequence in a charge trapping memory cell can also be produced from other materials. In conjunction with silicon oxide as limiting layers, the memory layer arranged in between may be, by way of example, a material from the group comprising tantalum oxide, hafnium silicate, titanium oxide (TiO2 in the case of stoichiometric composition), zirconium oxide (ZrO2 in the case of stoichiometric composition), alumina (Al2O3 in the case of stoichiometric composition) and intrinsically conductive silicon. The limiting layers used may also be oxynitride instead of oxide.
In future technologies, an oxynitride/Al2O3/oxynitride layer sequence is particularly preferred for the memory layer sequence of the charge trapping memory cells. Al2O3 can be etched other than by wet chemical means using conventional photomasks. It is also difficult to remove oxynitrides by wet chemical means using lacquer masks. The memory layer sequence therefore needs to be removed from the semiconductor body in the region of the actuation peripheral area by means of dry etching.